(a) Field of the Invention
The present invention relates to a method of forming a gate in a flash memory device, and more particularly, to a method of forming a gate in a flash memory device having advantages of enhancing an operation speed of a device by reducing resistance of a word line.
(b) Description of the Related Art
A NOR type of flash memory device is a non-volatile memory device having a floating gate and a control gate in its stacked structure. A stacked structure including a floating gate and a control gate is formed in a dual conductive polysilicon structure. The stacked structure is formed on a tunnel oxide layer. An ONO (Oxide—Nitride—Oxide) layer used as a dielectric layer is formed between a floating gate and a control gate. The ONO layer performs a function of a capacitor. A bias applied at a control gate can be applied at a floating gate through an ONO layer. A program operation and an erase operation for a flash memory device are performed by using a relatively high bias.
FIG. 1 is a top plan view showing a common source region of a conventional memory device. FIG. 2 is a cross-sectional view showing a method of forming a gate in a flash memory device.
Referring to FIG. 1, according to a conventional NOR flash memory device, a word line 20 is formed so as to cross a field oxide layer 17 defining an active region 11, and the word line 20 crosses a bit line. A single cell is formed at a crossing point between the word line 20 and the bit line. In addition, a bit line contact 31 and a drain contact are formed at an end of the active region 11.
The word line 20 adjacent to the bit line contact 31 has a different width from the word line 20 adjacent to a common source 15. The common source 15 has a single source contact for 16 cells. The common source 15 for 16 cells is connected with an N+ diffusion region.
In addition, STI (Shallow Trench Isolation) is used for isolation technology for a semiconductor device having a scale of 0.25 μm or 0.18 μm, and a self-aligned floating gate is formed in patterning a control gate in order to reduce a cell size of a semiconductor device having a scale of 0.35 μm or less. Even if STI and a self-aligned floating gate are used for reducing a cell size, resistance of a common source may be multiply increased by simultaneously using the STI and self-aligned floating gate.
Moreover, in a case that common source etching is used among several schemes for forming a common source, an oxide layer may be formed for stabilizing a gate after forming the common source. However, such an oxide layer may be non-uniformly formed due to plasma used in the common-source etching.
Referring to FIG. 2, according to a conventional method of forming a gate in a flash memory device, a field oxide layer 17 is formed on a semiconductor substrate by using STI. Subsequently, a tunnel oxide layer 22, a floating gate 21, a dielectric layer 24, and a control gate 25 are formed on a semiconductor substrate 10. In addition, when the control gate 25 is patterned, a self-aligned floating gate is also patterned.
After performing etching for patterning a gate 20, common source etching is performed in order to form the common source 15. The common source etching is performed for forming a trench 14 by selectively removing the field oxide layer 17 exposed by the gate 20 such that the semiconductor substrate 10 below the field oxide layer 17 is exposed by the trench 14.
Subsequently, the common source 15 is formed by forming a junction, such as an N+ diffusion layer, through ion implantation. The common source 15 performs a function of connecting between source regions of the device. Such common source etching is performed by using a SAS (Self Aligned Source) scheme. After forming the common source 15, an oxide layer 27 covering sidewalls of the gate 20 is formed through an oxidization or/and deposition process in order to stabilize the gate 20.
However, the oxide layer 27 may be non-uniformly formed due to plasma used in the common source etching. For example, the oxide layer 27 may have different thicknesses at sidewalls of the gate 20. More particularly, as shown in FIG. 2, a portion 41 of the oxide layer 27 may be formed with a relatively smaller thickness at the trench 14 for the common source 15 than a portion 43 of the oxide layer 27.
Such a non-uniform thickness of the oxide layer 27 may induce several problems. For example, resistance of the gate 20 may be undesirably increased due to the non-uniform thickness of the oxide layer 27. In addition, unstable electrons which are gathered in the floating gate 21 after programming a flash cell may escape through the portion 41 of the oxide layer 27 having the small thickness.
Moreover, a current ETOX (EEPROM Tunnel Oxide) type of device has the control gate 25 and the floating gate 21 in its dual polysilicon structure, and characteristics of such a flash memory device are determined by an erasing operation and a program operation. When a predetermined voltage is applied at a control gate, such a flash memory device may have a voltage applied at a floating gate through an ONO (Oxide-Nitride-Oxide) capacitor in a dielectric layer by using a coupling ratio.
At this time, since a plurality of cells 13 are formed in a single word line (referring to 20 in FIG. 1), the resistance of the gate 20 which composes the word line 20 may affect a current (IR) drop. Therefore, an undesired increase of the resistance of the gate 20 may induce the characteristic degradation of a flash memory device.
The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art.